What is the manufacturing process of SIC devices?
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As a long - standing SIC device supplier, I am very excited to share with you the manufacturing process of SIC (Silicon Carbide) devices. SIC devices have been making waves in the power electronics industry due to their superior performance characteristics, such as high breakdown voltage, low on - resistance, and excellent thermal conductivity compared to traditional silicon - based devices.
1. Raw Material Preparation
The first crucial step in the manufacturing of SIC devices is the preparation of high - quality SIC raw materials. The raw material for SIC devices is typically single - crystal Sic wafers. These wafers are produced through a complex process known as physical vapor transport (PVT).
In the PVT process, high - purity silicon carbide powder is placed in a graphite crucible. The crucible is then heated to extremely high temperatures, usually above 2000°C, in an inert gas atmosphere (such as argon). At these high temperatures, the silicon carbide powder sublimates, and the vapor condenses on a seed crystal placed at the cooler end of the crucible. Over time, a single - crystal Sic ingot grows on the seed crystal.
The quality of the single - crystal Sic ingot is of utmost importance as it directly affects the performance of the final SIC devices. Factors such as crystal defects, impurities, and lattice structure need to be carefully controlled during the growth process. After the ingot is grown, it is sliced into thin wafers using a diamond saw. These wafers are then polished to achieve a smooth and flat surface, which is essential for subsequent device fabrication processes.
2. Epitaxial Growth
Once the Sic wafers are prepared, the next step is epitaxial growth. Epitaxy is a process where a thin, single - crystal layer of Sic is grown on the surface of the Sic wafer. This epitaxial layer is designed to have specific electrical properties, such as doping concentration and thickness, which are crucial for the performance of the final SIC device.
Chemical vapor deposition (CVD) is the most commonly used method for Sic epitaxial growth. In the CVD process, a mixture of precursor gases, such as silane (SiH₄) and propane (C₃H₈), along with a dopant gas (such as nitrogen for n - type doping or aluminum for p - type doping), is introduced into a reaction chamber. The wafer is heated to a high temperature, typically around 1500 - 1600°C. The precursor gases decompose at the wafer surface, and the atoms are incorporated into the crystal lattice of the wafer, forming a high - quality epitaxial layer.
The control of the epitaxial growth process is very precise. Parameters such as gas flow rates, temperature, and pressure need to be carefully regulated to ensure the uniformity of the epitaxial layer in terms of thickness and doping concentration across the wafer.
3. Device Isolation
After the epitaxial growth, device isolation is carried out. The purpose of device isolation is to electrically isolate individual devices on the wafer, preventing electrical interference between adjacent devices.
One common method for device isolation in SIC devices is ion implantation. In ion implantation, high - energy ions are accelerated and implanted into the Sic epitaxial layer at specific locations. These ions create a highly resistive region in the epitaxial layer, effectively isolating adjacent devices. The type and energy of the ions, as well as the implantation dose and implantation angle, are carefully selected to achieve the desired isolation performance.
Another method for device isolation is trench isolation. In trench isolation, deep trenches are etched into the Sic epitaxial layer using reactive ion etching (RIE). The trenches are then filled with a dielectric material, such as silicon dioxide (SiO₂), to electrically isolate the devices. Trench isolation can provide better isolation performance, especially for high - voltage SIC devices.
4. Source and Drain Formation
Source and drain regions are essential components of SIC MOSFETs and other transistors. These regions are formed through a combination of ion implantation and annealing processes.
For n - type SIC devices, phosphorus or nitrogen ions are typically implanted into the epitaxial layer to create the source and drain regions. The implantation energy and dose are adjusted to achieve the desired doping concentration and depth. After ion implantation, the wafer is annealed at a high temperature, usually above 1600°C, to activate the implanted ions and repair the crystal damage caused by the implantation process.
The annealing process is critical as it affects the electrical properties of the source and drain regions, such as the resistivity and carrier mobility. Proper annealing can also improve the overall performance and reliability of the SIC device.
5. Gate Oxide Formation
In SIC MOSFETs, the gate oxide layer plays a crucial role in controlling the flow of current between the source and drain. The gate oxide is typically formed by thermal oxidation of the Sic surface.
The thermal oxidation process involves heating the Sic wafer in an oxygen - containing atmosphere at a high temperature. During the oxidation process, oxygen atoms react with the Sic surface to form a silicon dioxide (SiO₂) layer. However, the quality of the SiO₂/Sic interface is a major challenge in SIC MOSFETs. Defects at the interface can lead to high interface trap density, which can degrade the device performance, such as reducing the channel mobility and increasing the threshold voltage.
To improve the quality of the gate oxide and the SiO₂/Sic interface, various surface treatments and optimization techniques are used. For example, nitrogen annealing or the use of nitride - based gate oxides can help reduce the interface trap density and improve the device performance.
6. Metallization
Metallization is the process of depositing metal layers on the device to form electrical contacts and interconnects. In SIC devices, multiple metal layers are usually deposited.
The first metal layer, known as the ohmic contact metal, is deposited on the source, drain, and gate regions to form a low - resistance electrical contact. Metals such as titanium (Ti), nickel (Ni), and aluminum (Al) are commonly used for ohmic contacts. The ohmic contact metal is deposited using physical vapor deposition (PVD) methods, such as sputtering or evaporation. After the metal deposition, the wafer is annealed to form a stable ohmic contact.
Subsequent metal layers are deposited on top of the ohmic contact metal to form interconnects that connect different parts of the device. These metal layers are patterned using photolithography and etching techniques to create the desired circuit layout.
7. Packaging
After the fabrication process on the wafer is completed, the individual SIC devices are separated from the wafer using a dicing saw. These individual chips are then packaged into a suitable package to protect them from the environment and provide electrical connections.
There are various types of packages available for SIC devices, including surface - mount packages and through - hole packages. The choice of package depends on the application requirements, such as power dissipation, voltage rating, and physical size.
During the packaging process, the SIC chip is attached to a lead frame or a substrate using a conductive adhesive. Bond wires are then used to connect the chip pads to the package leads. Finally, the package is encapsulated with a molding compound to protect the chip from moisture, dust, and mechanical stress.
8. Testing and Quality Control
The final step in the manufacturing process of SIC devices is testing and quality control. Each packaged SIC device is tested to ensure that it meets the specified performance requirements.
Electrical tests are carried out to measure parameters such as breakdown voltage, on - resistance, threshold voltage, and switching characteristics. Thermal tests are also conducted to evaluate the device's thermal performance, such as the junction temperature and thermal resistance.
Based on the test results, the SIC devices are sorted into different grades according to their performance. Devices that do not meet the specification requirements are rejected, ensuring that only high - quality SIC devices are shipped to customers.
Throughout the manufacturing process, strict quality control measures are implemented to ensure the reliability and consistency of the SIC devices. This includes in - process inspections, material traceability, and statistical process control.
Conclusion
In conclusion, the manufacturing process of SIC devices is a complex and highly precise process that involves multiple steps, from raw material preparation to packaging and testing. Our company, as a professional SIC device supplier, is committed to using the most advanced manufacturing technologies and strict quality control systems to produce high - quality SIC devices that meet the diverse needs of our customers.
We offer a wide range of SIC devices, including Sic Schottky Diode and Sic Mosfet. If you are interested in our SIC devices or have any questions about their application and procurement, please feel free to contact us. We are looking forward to discussing your specific requirements and providing you with the best solutions.
References
- Baliga, B. J. (2005). Silicon Carbide Power Devices. World Scientific.
- Kimoto, T., & Cooper, J. A. (Eds.). (2014). Silicon Carbide: Materials, Processing, and Devices. Wiley - IEEE.
- Palmour, J. W., & Davis, R. F. (2000). Silicon Carbide: A Power Electronics Wonder Material. IEEE Transactions on Electron Devices, 47(3), 417 - 431.
